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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 8-bit, high speed, multiplying d/a converter (universal digital logic interface) dac08 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the dac08 series of 8-bit monolithic digital-to-analog convert- ers provide very high-speed performance coupled with low cost and outstanding applications flexibility. advanced circuit design achieves 85 ns settling times with very low glitch energy and at low power consumption. monotonic multiplying performance is attained over a wide 20 to 1 refer- ence current range. matching to within 1 lsb between refer- features fast settling output current: 85 ns full-scale current prematched to 6 1 lsb direct interface to ttl, cmos, ecl, htl, pmos nonlinearity to 0.1% maximum over temperature range high output impedance and compliance: C10 v to +18 v complementary current outputs wide range multiplying capability: 1 mhz bandwidth low fs current drift: 6 10 ppm/ 8 c wide power supply range: 6 4.5 v to 6 18 v low power consumption: 33 mw @ 6 5 v low cost available in die form ence and full-scale currents eliminates the need for full-scale trimming in most applications. direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic input. high voltage compliance complementary current outputs are provided, increasing versatility and enabling differential opera- tion to effectively double the peak-to-peak output swing. in many applications, the outputs can be directly converted to volt- age without the need for an external op amp. all dac08 series models guarantee full 8-bit monotonicity, and nonlinearities as tight as 0.1% over the entire operating tem- perature range are available. device performance is essentially unchanged over the 4.5 v to 18 v power supply range, with 33 mw power consumption attainable at 5 v supplies. the compact size and low power consumption make the dac08 attractive for portable and military/aerospace appli- cations; devices processed to mil-std-883, level b are available. dac08 applications include 8-bit, 1 m s a/d converters, servo motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, crt display drivers, high-speed modems and other applications where low cost, high speed and complete input/out- put versatility are required. functional block diagram
electrical characteristics dac08a/h dac08e dac08c parameter symbol conditions min typ max min typ max min typ max units resolution 8 8 8 bits monotonicity 8 8 8 bits nonlinearity nl 0.1 0.19 0.39 % fs settling time t s to 1/2 lsb, 85 135 85 150 85 150 ns all bits switched on or off, t a = 25 c 1 propagation delay each bit t plh t a = 25 c 1 35 60 35 60 35 60 ns all bits switched t phl 35 60 35 60 35 60 ns full-scale tempco 1 tci fs 10 50 10 80 10 80 ppm/ c dac08e 50 output voltage compliance v oc full-scale current (true compliance) change <1/2 lsb, C10 +18 C10 +18 C10 +18 v r out > 20 m w typ full range current i fr4 v ref = 10.000 v 1.984 1.992 2.000 1.94 1.99 2.04 1.94 1.99 2.04 ma r14, r15 = 5.000 k w t a = +25 c full range symmetry i frs i fr4 C i fr2 0.5 4 1 8 2 16 m a zero-scale current i zs 0.1 1 0.2 2 0.2 4 m a output current range i or1 r14, r15 = 5.000 k w 2.1 2.1 2.1 ma i or2 v ref = +15.0 v, vC = C10 v v ref = +25.0 v, 4.2 4.2 4.2 ma vC = C12 v output current noise i ref = 2 ma 25 25 25 na logic input levels logic 0 v il v lc = 0 v 0.8 0.8 0.8 v logic input 1 v il 22 2 v logic input current v lc = 0 v logic 0 i il v in = C10 v to +0.8 v C2 C10 C2 C10 C2 C10 m a logic input 1 i ih v in = 2.0 v to 18 v 0.002 10 0.002 10 0.002 10 m a logic input swing v is vC = C15 v C10 +18 C10 +18 C10 +18 v logic threshold range v thr v s = 15 v 1 C10 +13.5 C10 +13.5 C10 +13.5 v reference bias current i 15 C1 C3 C1 C3 C1 C3 m a reference input di/dt r eq = 200 w 4 8 4 8 4 8 ma/ m s slew rate r l = 100 w c c = 0 pf see fast pulsed ref. info following. 1 power supply sensitivity pssi fs+ v+ = 4.5 v to 18 v 0.0003 0.01 0.0003 0.01 0.0003 0.01 % d i o /% d v+ pssi fsC vC = C4.5 v to C18 v 0.002 0.01 0.002 0.01 0.002 0.01 % d i o /% d vC i ref = 1.0 ma power supply current i+ v s = 5 v, i ref = 1.0 ma 2.3 3.8 2.3 3.8 2.3 3.8 ma iC C4.3 C5.8 C4.3 C5.8 C4.3 C5.8 ma i+ v s = +5 v, C15 v, 2.4 3.8 2.4 3.8 2.4 3.8 ma iC i ref = 2.0 ma C6.4 C7.8 C6.4 C7.8 C6.4 C7.8 ma i+ v s = 15 v, i ref = 2.5 3.8 2.5 3.8 2.5 3.8 ma iC 2.0 ma C6.5 C7.8 C6.5 C7.8 C6.5 C7.8 ma power dissipation p d 5 v, i ref = 1.0 ma 33 48 33 48 33 48 mw +5 v, C15 v, i ref = 2.0 ma 108 136 103 136 108 136 mw 15 v, i ref = 2.0 ma 135 174 135 174 135 174 mw notes 1 guaranteed by design. specifications subject to change without notice. rev. a C2C (@ v s = 6 15 v, i ref = 2.0 ma, C55 8 c t a +125 8 c for dac08/08a, 0 8 c t a +70 8 c for dac08c, e & h unless otherwise noted. output characteristics refer to both i out and i out .) dac08Cspecifications
pin connections 16-pin dual-in-line package (q suffix) 16-lead so (s suffix) dac08rc/883 20-lead lcc (rc suffix) nc = no connect absolute maximum ratings 1 operating temperature dac08aq, q . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c dac08hq, eq, cq, hp, ep, cp, cs . . . . . 0 c to +70 c junction temperature (t j ) . . . . . . . . . . . . . . C65 c to +150 c storage temperature q package . . . . . . . . . . C65 c to +150 c storage temperature p package . . . . . . . . . . C65 c to +125 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . . 300 c v+ supply to vC supply . . . . . . . . . . . . . . . . . . . . . . . . . . 36 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . vC to vC plus 36 v v lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vC to v+ analog current outputs (at v s C = 15 v) . . . . . . . . . . 4.25 ma reference input (v 14 to v 15 ) . . . . . . . . . . . . . . . . . . . vC to v+ reference input differential voltage (v 14 to v 15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v reference input current (i 14 ) . . . . . . . . . . . . . . . . . . . 5.0 ma package type u ja 2 u jc units 16-pin hermetic dip (q) 100 16 c/w 16-pin plastic dip (p) 82 39 c/w 20-contact lcc (rc) 76 36 c/w 16-pin so (s) 111 35 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket for cerdip, p-dip, and lcc packages; q ja is specified for device soldered to printed circuit board for so package. ordering guide 1 16-pin dual-in-line package operating temperature nl hermetic plastic lcc range 0.1% dac08aq 2 mil dac08hq dac08hp com 0.19% dac08q 2 dac08rc/883 mil dac08eq dac08ep com 0.39% dac08cq dac08cp com dac08cs 3 com notes 1 burn-in is available on commercial and industrial temperature range parts in cerdip, plastic dip, and to-can packages. 2 for devices processed in total compliance to mil-std-883, add /883 after part number. consult factory for 883 data sheet. 3 for availability and burn-in information on so and plcc packages, contact your local sales office. typical electrical characteristics all grades parameter symbol conditions typical units reference input slew rate di/dt 8 ma/ m s propagation delay t plh , t phl t a = 25 c, any bit 35 ns settling time t s to +1/2 lsb, all bits switched on or off, 85 ns t a = 25 c notes for dac08nt & gt 25 c characteristics, see dac08n & g characteristics respectively. specifications subject to change without notice (@ v s = 6 15 v, and i ref = 2.0 ma, unless otherwise noted. output characteristics apply to both i out and i out .) dac08 C3C rev. a
dac08 C4C rev. a wafer test limits dac08nt dac08n dac08gt dac08g dac08gr parameter symbol conditions limit limit limit limit limit units resolution 8 8 8 8 8 bits min monotonicity 8 8 8 8 8 bits min nonlinearity nl 0.1 0.1 0.19 0.19 0.39 % fs max output voltage v oc full-scale current +18 +18 +18 +18 +18 v max compliance change < 1/2 lsb C10 C10 C10 C10 C10 v min full-scale current i fs4 or v ref = 10.000 v 2.04 2.04 2.04 2.04 2.04 ma max i fs2 r 14 , r 15 = 5.000 k w 1.94 1.94 1.94 1.94 1.94 ma min full-scale symmetry i fss 8 8 8 8 16 m a max zero-scale current i zs 22444 m a max output current range i fs1 vC = C10 v, v ref = +15 v 2.1 2.1 2.1 2.1 2.1 ma min vC = C12 v, i fs2 v ref = +25 v 4.2 4.2 4.2 4.2 4.2 ma min r 14 , r 15 = 5.000 k w logic input 0 v il 0.8 0.8 0.8 0.8 0.8 v max logic input 1 v ih 2 2 2 2 2 v min logic input current v lc = 0 v logic 0 i il v in = C10 v to +0.8 v 10 10 10 10 10 m a max logic 1 i ih v in = 2.0 v to 18 v 10 10 10 10 10 m a max logic input swing v is vC = C15 v +18 +18 +18 +18 +18 v max C10 C10 C10 C10 C10 v min reference bias current i 15 C3 C3 C3 C3 C3 m a max power supply pssi fs+ v+ = 4.5 v to 18 v 0.01 0.01 0.01 0.01 0.01 % fs/% v max sensitivity pssi fsC vC = C4.5 v to C18 v i ref = 1.0 ma power supply current i+ v s = 15 v 3.8 3.8 3.8 3.8 3.8 ma max i ref 2.0 ma C7.8 C7.8 C7.8 C7.8 C7.8 m a max power dissipation p d v s = 15 v 174 174 174 174 174 mw max i ref 2.0 ma note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. dice characteristics (+125 c tested dice available) (@ v s = 6 15 v, i ref = 2.0 ma, t a = 125 8 c for dac08nt, dac08gt devices; t a = 25 8 c for dac08n, dac08g and dac08gr devices, unless otherwise noted. output characteristics apply to both i out and i out .)
dac08 C5C rev. a figure 4. true and complimentary output operation figure 6. full-scale settling time figure 5. lsb switching figure 3. fast pulsed reference operation figure 1. pulsed reference operation figure 2. burn-in circuit
dac08 C6C rev. a Ctypical performance characteristics figure 7. full-scale current vs. reference current figure 10. reference amp common-mode range figure 13. output current vs. output voltage (output voltage compliance) figure 8. lsb propagation delay vs. i fs figure 11. logic input current vs. input voltage figure 14. output voltage compliance vs. temperature figure 9. reference input frequency response figure 12. v th Cv lc vs. temperature figure 15. bit transfer characteristics
dac08 C7C rev. a figure 16. power supply current vs. v+ figure 17. power supply current vs. vC figure 18. power supply current vs. temperature basic connections figure 19. accomodating bipolar references figure 20. basic positive reference operation figure 21. basic unipolar negative operation
dac08 C8C rev. a figure 22. basic bipolar output operation figure 23. recommended full-scale adjustment circuit figure 24. basic negative reference operation figure 25. offset binary operation
dac08 C9C rev. a applications information reference amplifier set-up the dac08 is a multiplying d/a converter in which the output current is the product of a digital number and the input refer- ence current. the reference current may be fixed or may vary from nearly zero to +4.0 ma. the full-scale output current is a linear function of the reference current and is given by: i fr = 255 256 i ref , where i ref = i 14 . in positive reference applications, an external positive reference voltage forces current through r14 into the v ref(+) terminal (pin 14) of the reference amplifier. alternatively, a negative ref- erence may be applied to v ref(C) at pin 15; reference current flows from ground through r14 into v ref(+) as in the positive reference case. this negative reference connection has the ad- vantage of a very high impedance presented at pin 15. the volt- age at pin 14 is equal to and tracks the voltage at pin 15 due to the high gain of the internal reference amplifier. r15 (nominally equal to r14) is used to cancel bias current errors; r15 may be eliminated with only a minor increase in error. bipolar references may be accommodated by offsetting v ref or pin 15. the negative common-mode range of the reference am- plifier is given by: v cm C = vC plus (i ref 1 k w ) plus 2.5 v. the positive common-mode range is v+ less 1.5 v. when a dc reference is used, a reference bypass capacitor is rec- ommended. a 5.0 v ttl logic supply is not recommended as a refere nce. if a regulated power supply is used as a reference, r14 should be split into two resistors with the junction bypassed to ground with a 0.1 m f capacitor. for most applications the tight relationship between i ref and i fs will eliminate the need for trimming i ref . if required, full-scale trimming may be accomplished by adjusting the value of r14, or by using a potentiometer for r14. an improved method of full-scale trimming which eliminates potentiometer t.c. effects is shown in the recommended full-scale adjustment circuit. using lower values of reference current reduces negative power supply current and increases reference amplifier negative common- mode range. the recommended range for operation with a dc reference current is +0.2 ma to +4.0 ma. figure 27. negative low impedance output operation figure 26. positive low impedance output operation figure 28. interfacing with various logic families
dac08 C10C rev. a reference amplifier compensation for multiplying applications ac reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to vC. the value of this capacitor depends on the impedance presented to pin 14: for r14 values of 1.0, 2.5 and 5.0 k w , minimum values of c c are 15, 37, and 75 pf. larger values of r14 require proportion- ately increased values of c c for proper phase margin, such that the ratio of c c (pf) to r14 (k w ) = 15. for fastest response to a pulse, low values of r14 enabling small c c values should be used. if pin 14 is driven by a high imped- ance such as a transistor current source, none of the above val- ues will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. for r14 = 1 k w and c c = 15 pf, the reference amplifier slews at 4 ma/ m s enabling a transition from i ref = 0 to i ref = 2 ma in 500 ns. operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. this technique provides lowest full-scale transition times. an internal clamp allows quick recovery of the reference amplifier from a cutoff (i ref = 0) condition. full-scale transition (0 ma to 2 ma) occurs in 120 ns when the equivalent impedance at pin 14 is 200 w and c c = 0. this yields a reference slew rate of 16 ma/ m s which is relatively independent of r in and v in values. logic inputs the dac08 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. this feature is made pos- sible by the large input swing capability, 2 m a logic input cur- rent and completely adjustable logic threshold voltage. for vC = C15 v, the logic inputs may swing between C10 v and +18 v. this enables direct interface with +15 v cmos logic, even when the dac08 is powered from a +5 v supply. minimum in- put logic swing and minimum logic threshold voltage are given by: vC plus ( i ref 1 k w ) plus 2.5 v. the logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (pin 1, v lc ). the appropriate graph shows the relationship between v lc and v th over the temperature range, with v th nominally 1.4 above v lc . for ttl and dtl interface, simply ground pin 1. when interfacing ecl, an i ref = 1 ma is recommended. for interfacing other logic families, see preceding page. for general set-up of the logic control circuit, it should be noted that pin 1 will source 100 m a typical; external circuitry should be designed to accommodate this current. fastest settling times are obtained when pin 1 sees a low imped- ance. if pin 1 is connected to a 1 k w divider, for example, it should be bypassed to ground by a 0.01 m f capacitor. analog output currents both true and complemented output sink currents are provided where i o + i o = i fs . current appears at the true (i o ) output when a 1 (logic high) is applied to each logic input. as the bi- nary count increases, the sink current at pin 4 increases propor- tionally, in the fashion of a positive logic d/a converter. when a 0 is applied to any input bit, that current is turned off at pin 4 and turned on at pin 2. a decreasing logic count increases i o as in a negative or inverted logic d/a converter. both outputs may be used simultaneously. if one of the outputs is not required it must be connected to ground or to a point capable of sourcing i fs ; do not leave an unused output pin open. both outputs have an extremely wide voltage compliance en- abling fast direct current-to-voltage conversion through a resis- tor tied to ground or other voltage source. positive compliance is 36 v above vC and is independent of the positive supply. negative compliance is given by vC plus (i ref 1 k w ) plus 2.5 v. the dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. this fea- ture is especially useful in cable driving, crt deflection and in other balanced applications such as driving center-tapped coils and transformers. power supplies the dac08 operates over a wide range of power supply volt- ages from a total supply of 9 v to 36 v. when operating at sup- plies of 5 v or less, i ref 1 ma is recommended. low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range, and negative logic threshold range; consult the various figures for guidance. for example, operation at C4.5 v with i ref = 2 ma is not rec- ommended because negative output compliance would be re- duced to near zero. operation from lower supplies is possible, however at least 8 v total must be applied to insure turn-on of the internal bias network. symmetrical supplies are not required, as the dac08 is quite insensitive to variations in supply voltage. battery operation is feasible as no ground connection is required: however, an artifi- cial ground may be used to insure logic swings, etc. remain be- tween acceptable limits. power consumption may be calculated as follows: p d = (i+) (v+) + (iC) (vC). a useful feature of the dac08 design is that supply current is constant and independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of the power supply bypass capacitors. temperature performance the nonlinearity and monotonicity specifications of the dac08 are guaranteed to apply over the entire rated operating tempera- ture range. full-scale output current drift is low, typically 10 ppm/ c, with zero-scale output current and drift essentially negligible compared to 1/2 lsb. the temperature coefficient of the reference resistor r14 should match and track that of the output resistor for minimum overall full-scale drift. settling times of the dac08 decrease approxi- mately 10% at C55 c; at +125 c an increase of about 15% is typical. the reference amplifier must be compensated by using a capaci- tor from pin 16 to vC. for fixed reference operation, a 0.01 m f capacitor is recommended. for variable reference applications, see previous section entitled reference amplifier compensa- tion for multiplying applications.
dac08 C11C rev. a multiplying operation the dac08 provides excellent multiplying performance with an extremely linear relationship between i fs and i ref over a range of 4 ma to 4 ma. monotonic operation is maintained over a typical range of i ref from 100 m a to 4.0 ma. settling time the dac08 is capable of extremely fast settling times, typically 85 ns at i ref = 2.0 ma. judicious circuit design and careful board layout must be employed to obtain full performance po- tential during testing and application. the logic switch design enables propagation delays of only 35 ns for each of the 8 bits. settling time to within 1/2 lsb of the lsb is therefore 35 ns, with each progressively larger bit taking successively longer. the msb settles in 85 ns, thus determining the overall settling time of 85 ns. settling to 6-bit accuracy requires about 65 ns to 70 ns. the output capacitance of the dac08 including the package is approximately 15 pf, therefore the output rc time constant dominates settling time if r l > 500 w . settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. settling time also remains essentially constant for i ref values. the principal advantage of higher i ref values lies in the ability to attain a given output level with lower load resistors, thus reducing the output rc time constant. measurement of settling time requires the ability to accurately resolve 4 m a, therefore a 1 k w load is needed to provide ad- equate drive for most oscilloscopes. the settling time fixture shown in schematic labelled settling time measurement uses a cascode design to permit driving a 1 k w load with less than 5 pf of parasitic capacitance at the measurement node. at i ref values of less than 1.0 ma, excessive rc damping of the output is difficult to prevent while maintaining adequate sensitivity. however, the major carry from 01111111 to 10000000 provides an accurate indicator of settling time. this code change does not require the normal 6.2 time constants to settle to within 0.2% of the final value, and thus settling times may be ob- served at lower values of i ref . dac08 switching transients or glitches are very low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time. fastest operation can be obtained by using short leads, minimiz- ing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and v lc terminals. supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 m f capaci- tors at the supply pins provide full transient protection. figure 30. settling time measurement
dac08 C12C rev. a outline dimensions dimensions shown in inches and (mm). 000000000 printed in u.s.a. n-16 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) q-16 16 1 8 9 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.080 (2.03) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) e-20 top view 0.358 (9.09) 0.342 (8.69) sq 1 20 4 9 8 13 19 bottom view 14 3 18 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) bsc 0.200 (5.08) bsc 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) so-16 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
package/price information for detailed packaging information, please select the datasheets button. 8-bit, high speed, multiplying d/a converter (universal digital logic interface) ?model? status package description pin count temperature range price* (100-499) ?5962-89932012a? ?production? ?cer. leadless chip carrier? ?20? ?tbd? ?$31.68? ?dac08aq? ?production? ?cerdip glass seal? ?16? ?military? ?$6.05? ?dac08aq/883c? ?production? ?cerdip glass seal? ?16? ?military? ?$8.25? ?dac08cp? ?production? ?plastic/epoxy dip? ?16? ?military? ?$1.20? ?dac08cq? ?production? ?cerdip glass seal? ?16? ?military? ?$1.38? ?dac08cs? ?production? ?std s.o. pkg (soic)? ?16? ?military? ?$1.20? ?dac08ep? ?production? ?plastic/epoxy dip? ?16? ?commercial? ?$1.50? ?dac08eq? ?production? ?cerdip glass seal? ?16? ?industrial? ?$1.87? ?dac08es? ?production? ?std s.o. pkg (soic)? ?16? ?commercial? ?$1.50? ?dac08gbc? ?production? ?chips/die sales? - ?tbd? ?$1.20? ?dac08grbc? ?production? ?chips/die sales? - ?tbd? ?$0.82? ?dac08gtbc? ?obsolete? ?chips/die sales? - ?tbd? - ?dac08hp? ?production? ?plastic/epoxy dip? ?16? ?commercial? ?$2.25? ?dac08hq? ?production? ?cerdip glass seal? ?16? ?military? ?$2.75? ?dac08nbc? ?production? ?chips/die sales? - ?tbd? ?$1.90? ?dac08ntbc? ?production? ?chips/die sales? - ?tbd? ?$4.00? ?dac08q? ?production? ?cerdip glass seal? ?16? ?tbd? ?$4.40? ?dac08q/883c? ?production? ?cerdip glass seal? ?16? ?tbd? ?$6.60? ?dac08rc/883c? ?production? ?cer. leadless chip carrier? ?20? ?tbd? ?$23.80? ?jm38510/11301bea? ?production? ?cerdip glass seal? ?16? ?military? ?$16.50? * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability (currently available to north american customers) for further information. analog products -- dac08 file:///f|/cpl_new_images/dac08.html [7/18/2001 5:35:55 pm]

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